Design of a Computational Floating Point Mathematical Coprocessor on FPGA using VHDL
نویسندگان
چکیده
This paper deals with the design of a mathematical coprocessor using RISC based approach. The coprocessor can relieve the main processor of large matrix based computations usually used in the field of image processing, cryptography, etc. The protocol for communication of the processor with the computer is also designed in the project. The timing required for the designed processor is checked with a Visual Basic interface. The main processor can transmit matrix values to the coprocessor, which can return the main processor with the desired results. The mathematical coprocessor was implemented on Spartan III Field Programmable Gate Array using VHDL Keywords—Coprocessor, Computational, Floating Point, FPGA, Matrix
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